Projects

Building systems

Research and build work across embedded, RF, and systems.

Selected projects spanning SoC design, embedded systems, and interactive hardware.

Focus areas

  • Computer ArchitectureRISC-V / ASIC
  • HW/SW Co-DesignFPGA Acceleration
  • Embedded systemsRTOS / Baremetal
  • Hardware EngineeringPCB Architecture

Research & Project Work

Pipelined RISC-V Processor Design

January 2026 - Present
RV32IM SystemVerilog / RTL Data cache Branch prediction Verilator FPGA ByPass Data Hazard
  • Architected a custom pipelined RV32IM RISC-V core with an integrated data cache in SystemVerilog.
  • Engineered branch prediction, out-of-order execution, and bypass/stall logic to resolve pipeline data hazards.
  • Synthesized RTL with Yosys to FPGA and validated logic via Verilator testbenches and waveform debug.

TSMC 45nm RISC-V SoC Tape-Out

January 2026 - Present
Chipyard RTL-to-GDSII mflowgen TSMC 45nm Innovus IR drop Clock Tree
  • Generated custom RISC-V SoC RTL using Chipyard generators to drive the physical design pipeline.
  • Engineered an RTL-to-GDSII workflow with mflowgen, migrating from Foundation to Cadence Stylus flow.
  • Executing full-chip synthesis and PnR on TSMC 45nm with Calibre/Innovus, validating IR drop and cross clock domains.

System-on-a-Chip Architecture: ARM+FPGA LZW Compression

August - December 2025
SoC Architecture Ultra96/Zynq FPGA ARM NEON Vitis HLS DMA
  • Mapped a CDC→SHA-256→Dedup→LZW pipeline across ARM cores and FPGA fabric for real-time compression.
  • Achieved ~200 Mb/s throughput during demo with FPGA LZW offload and validated end-to-end correctness.
  • Reported compression ratios up to ~1.96× on large files and documented system bottlenecks in data movement.

Spectrum Analyzer SoC Design and Tape-out (TSMC 180nm)

January - December 2025
Analog IC RF Cadence Virtuoso PEX TSMC 180nm
  • Designed a full-chip spectrum analyzer integrating PLL, mixer, filters, and I/O in Cadence Virtuoso on TSMC 180nm.
  • Implemented analog/mixed-signal IPs including PLL, passive mixer, S/D converters, low-pass filter, and memory block.
  • Validated blocks via PEX simulations; built testbench and measurement plan for chip specs.

Pipeline ADC Design (1-bit per stage)

August - December 2025
Mixed-signal ADC design MATLAB Comparator/DAC Verification
  • Designed an 8-bit pipeline ADC (1-bit/stage) with clean bit alignment and simplified stage-level debugging.
  • Built and verified key subblocks—T/H, comparator, DAC, and gain stages—meeting 2 MHz rate and >43 dB SNDR.
  • Validated via MATLAB INL/DNL/FFT; achieved 6.91 ENOB and 0.84 W power, analyzed FOM.

Configurable Logic Block (CLB) Design & Optimization

August - December 2024
Digital IC SRAM LUT Cadence 45nm DRC/LVS
  • Designed a CLB in Cadence 45nm integrating a 16:1 LUT using SRAM, muxes, and control logic.
  • Optimized LUT with internal inverters, transistor sizing, and SRAM precharge circuitry.
  • Achieved 784.313 MHz, 723600 nm², and 2.2904 pJ; full DRC/LVS compliance.

RTOS-Implementation on custom 4-Layer PCB

January - May 2025
PCB design SAMD21 FreeRTOS I2C Node-RED
  • Designed a 4-layer PCB with SAMD21 and WINC1500 (PCBWAY) for automated plant monitoring/irrigation.
  • Integrated soil, air, and NPK sensors with motor, pump, and buzzer over I2C using FreeRTOS.
  • Built a Node-RED dashboard for remote control/alerts; improved irrigation and reduced water use by 25%.

Real-Time Wireless Gesture-Control Wearable

August - December 2024
Embedded C IMU Zigbee MIDI Sensor fusion
  • Built a wearable mapping hand gestures and motion to MIDI control using IMU, LCDs, and sensor fusion.
  • Used ADXL335 accelerometers, Neopixel rings, Zigbee (XBee S2C), ATMega32PB, and a custom Python MIDI bridge.
  • Enabled low-latency gesture recognition and audio control via interrupt-driven sampling and SPI/LCD integration.